High-density interconnect (HDI) PCBs have moved from exotic aerospace projects into everyday automotive, medical, telecom, and industrial electronics. Dense ball-grid arrays, shrinking enclosures, and faster signal speeds now demand laser-drilled microvias, fine lines, thin dielectrics, and sequential lamination. In this environment, CAD software is not just a drawing tool. It becomes the central decision-making platform where stackup geometry, routing density, electrical performance, and manufacturability must all converge. Designing for HDI requires a different mindset than conventional through-hole PCB design. Every pad, via, and layer transition has to be modeled with fabrication limits in mind. This guide walks through the essential CAD workflow for HDI PCB design, from configuring the stackup to generating fabrication data that avoids costly revisions.
1. Configuring the HDI Stackup and CAD Design Rules
HDI design begins in the CAD stackup manager, not in the schematic. Before placing components or routing, you need to define the exact layer architecture: 1+N+1, 2+N+2, or any-layer construction. The “N” represents the core layers, which are typically standard FR-4 or low-loss laminates. The outer microvia layers use thin prepregs and copper foils that support laser drilling and precise impedance control. If you model the wrong dielectric thickness, your impedance calculations, insertion loss estimates, and laser aspect ratios will be incorrect from the start. This is why modern CAD tools such as Altium Designer, Cadence Allegro, and Siemens Xpedition encourage designers to create a detailed cross-section before any layout work begins.
Define microvia design rules as early as possible. A microvia is generally a laser-drilled hole with a diameter of 0.1 mm or smaller on the outer layer. Its pad diameter is often 0.2 mm to 0.3 mm, and the aspect ratio is usually 1:1 or less. These dimensions vary by fabricator, but the CAD tool must enforce them through dedicated via definitions. Create separate via types for each layer span, such as L1-L2, L2-L3, and L1-L3. This prevents a standard through-hole via from being placed where it would violate sequential lamination or laser depth capability. For example, a blind via from L1 to L2 should not be allowed to continue drilling deeper into the board unless the stackup and fabrication process explicitly support it.
Set up annular ring rules, capture pads, and laser target pads in your padstack editor. Many HDI fabricators prefer a laser target pad on the layer below a microvia to improve drill alignment. In CAD, this means modeling the microvia as a padstack with different pad diameters on the start and target layers. It is a small detail that has a big impact on manufacturing yield. Also define line width and spacing constraints based on the fabricator’s etching capabilities. HDI boards commonly use 75 µm traces and spaces, but advanced designs may require 50 µm. Entering these values into the constraint manager before routing prevents overoptimistic traces that cannot be produced reliably.
Material parameters are equally important. Populate the CAD material library with accurate Dk and Df values at your operating frequencies. HDI boards often combine standard FR-4 cores with low-loss prepregs, especially in high-speed or RF designs. Wrong material parameters can shift differential impedance and increase signal loss. A well-configured stackup also drives thermal behavior, crosstalk analysis, and final cost. When the stackup is complete, it becomes the single source of truth for every routing and simulation decision that follows.
2. Floorplanning, Microvia Fanout, and Escape Routing in CAD
HDI layout success depends heavily on the first routing steps. Start by placing large BGAs, connectors, power devices, and high-speed components in their final positions. Then use the CAD tool’s fanout utilities to create microvia-based escapes. For a 0.5 mm pitch BGA, a dog-bone fanout with a laser microvia in the pad or offset from the pad is common. For 0.4 mm pitch and below, via-in-pad with filled and capped microvias becomes essential. Define different fanout strategies for signal, power, and ground pins. Power and ground pins often need multiple microvias or larger buried vias to reduce inductance, while signal pins require controlled impedance and minimal stub length.
One of the biggest mistakes in HDI design is treating fanout as simple via placement. In CAD, you must account for sequential lamination order. If the design uses a 2+N+2 stackup, a via from L1 to L2 can be stacked or staggered with a via from L2 to L3. Stacked microvias provide shorter electrical paths but require precise laser alignment, copper filling, and planarization. Staggered structures are easier to fabricate but consume more routing space. Use the CAD via stack editor to define allowed combinations. If a buried via must be filled and plated over before creating the next microvia layer, the padstack definition should reflect that requirement. Otherwise, you may create a design that cannot survive the lamination cycle.
Escape routing should proceed layer by layer. On the outer microvia layer, route a short trace from the SMD pad to the microvia. The signal then drops to the next layer and routes beneath the BGA. The CAD constraint manager should enforce minimum trace width, spacing, and via-to-trace clearance. Many designers use neck-down routing only where necessary, because reducing trace width too much can create impedance discontinuities. For high-speed differential pairs, integrate the CAD router with the impedance calculator. If a pair requires 100 ohms differential, the tool should automatically adjust width and spacing based on the stackup. This is where How to Design for HDI PCB Using CAD Software becomes a practical reference for setting up fanout rules that align with real fabrication limits.
Power distribution also changes in HDI layouts. Large continuous power planes may be impossible because of dense signal routing and layer cutouts. Use CAD to create dedicated power islands and small pours on signal layers, and assign multiple microvias to high-current rails. This reduces loop inductance and improves thermal performance. At the same time, keep ground pours as continuous as possible. A broken return path can degrade signal integrity and increase EMI. When every millimeter matters, the floorplan and fanout phase should be the most disciplined part of the design process.
3. Design Validation, DFM Checks, and CAD Output Generation
After routing, the difference between a working prototype and a board that cannot be manufactured often lies in CAD validation. Run a full design rule check with manufacturer-specific rules: minimum annular ring, solder mask dam width, copper-to-edge clearance, laser via capture pad, and drill-to-copper spacing. Generic DRC settings are not enough for HDI. A trace-and-space value that passes your default rules may still fail the fabricator’s etching tolerance if the etch factor is not included. Adjust the DRC matrix to match the fabricator’s process capabilities. Many HDI manufacturers provide rule decks or design guidelines that can be imported directly into popular CAD tools.
Use the CAD tool’s 3D viewer and cross-section editor to inspect the layer stack. Verify that blind vias land exactly on internal pads and that there is no unintended overlap. Staggered microvias need enough clearance between the L1-L2 via and the L2-L3 via. Stacked microvias need filled copper and flat pads. If the CAD model does not show a planar surface over a buried via, there may be a void that traps process chemistry or causes a weak solder joint. This is especially critical for via-in-pad technology used under fine-pitch BGAs. In your CAD padstack definition, mark those vias as filled and capped if required, and include the cap thickness in the layer stack. Fabricators rely on this information to plan laser drilling, plating, and planarization steps.
Run signal and power integrity checks inside CAD where possible. Even basic tools can highlight high-current bottlenecks, missing bypass capacitors, and long return loops. For high-frequency boards, simulate critical nets using the CAD tool’s integrated field solver or export the stackup to an external simulator. HDI boards for telecom, aerospace, and automotive systems often combine high-speed digital, RF, and analog circuits. These mixed-signal designs need carefully partitioned planes and shielding. Use keepout zones, shape separation, and net classes to prevent digital noise from coupling into sensitive analog nodes. The dense routing of HDI makes this more difficult, so validation is not optional.
When the design passes DRC and simulation, generate the manufacturing outputs carefully. Produce Gerber files, NC drill files, and a detailed fabrication drawing. State the stackup, material types, copper weights, via types, and special requirements such as laser via filling or controlled impedance. Include a separate microvia drill file if your CAD tool does not merge blind and buried drill data automatically. Clearly mark the different drill spans: through-hole, L1-L2, L2-L3, and so on. Many HDI fabrication delays occur because drill files lack layer span information. If the manufacturer supports IPC-2581 or ODB++, prefer those formats because they preserve net information and stackup details better than Gerber alone. Then review the bill of materials and assembly data. HDI boards use fine-pitch components that require precise solder mask alignment and paste mask control. In CAD, define solder mask expansion values based on pad size, and check paste mask openings for micro-BGAs and land grid arrays. A successful HDI design is not only about routing density; it is about generating data that clearly communicates every critical detail to the fabricator and assembler.
A Sarajevo native now calling Copenhagen home, Luka has photographed civil-engineering megaprojects, reviewed indie horror games, and investigated Balkan folk medicine. Holder of a double master’s in Urban Planning and Linguistics, he collects subway tickets and speaks five Slavic languages—plus Danish for pastry ordering.